/*
  ******************************************************************************
  * @file    apt32f172.c
  * @author  APT AE Team
  * @version V1.12
  * @date    2019/03/08
  ******************************************************************************
  *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES 
  *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
  *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, 
  *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF 
  *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION 
  *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES 
  *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "apt32f172.h"

/**
  * @addtogroup Struct pointer assignment Functions
  * @{
  */
CSP_CK801_T   *CK801 = (CSP_CK801_T   *)CK801_BASEADDR ;

CSP_IFC_T   *IFC     = (CSP_IFC_T    *)APB_IFCBase ;
CSP_SYSCON_T *SYSCON = (CSP_SYSCON_T *)APB_SYSCONBase ;

CSP_TKEY_T  *TKEY    = (CSP_TKEY_T  *)APB_TKEYBase ;
CSP_ADC12_T *ADC0    = (CSP_ADC12_T  *)APB_ADC0Base ;

CSP_GPIO_T  *GPIOA0   = (CSP_GPIO_T  *)APB_GPIOA0Base ; // A0
CSP_GPIO_T  *GPIOA1   = (CSP_GPIO_T  *)APB_GPIOA1Base ; // A1
CSP_GPIO_T  *GPIOB0   = (CSP_GPIO_T  *)APB_GPIOB0Base ; // B0
CSP_GPIO_T  *GPIOC0   = (CSP_GPIO_T  *)APB_GPIOC0Base ; // C0
CSP_GPIO_T  *GPIOD0   = (CSP_GPIO_T  *)APB_GPIOD0Base ; // D0
CSP_IGRP_T  *EXIGRP   = (CSP_IGRP_T  *)APB_IGRPBase ;   // EXI GROUP CONTROL

CSP_GPT3C_T   *GPT      = (CSP_GPT3C_T   *)APB_GPTBase ;
CSP_GPT_T   *GPTCH0      = (CSP_GPT_T   *)APB_GPTCH0Base ;
CSP_GPT_T   *GPTCH1      = (CSP_GPT_T   *)APB_GPTCH1Base ;
CSP_GPT_T   *GPTCH2      = (CSP_GPT_T   *)APB_GPTCH2Base ;
CSP_GTC_T   *GTC      = (CSP_GTC_T   *)APB_GTCBase ;
CSP_ST16_T  *ST16     = (CSP_ST16_T  *)APB_ST16Base ;
CSP_CTC_T   *CTC      = (CSP_CTC_T   *)APB_CTCBase ;
CSP_EPWM_T  *EPWM     = (CSP_EPWM_T  *)APB_EPWMBase ;

CSP_LED_T   *LED0     = (CSP_LED_T   *)APB_LED0Base ;

CSP_USART_T *USART0   = (CSP_USART_T *)APB_USART0Base ;
CSP_UART_T  *UART1    = (CSP_UART_T  *)APB_UART1Base ;
CSP_SSP_T   *SPI0     = (CSP_SSP_T   *)APB_SPI0Base ;
CSP_I2C_T   *I2C0     = (CSP_I2C_T   *)APB_I2C0Base ;
CSP_CMP_T   *CMP      = (CSP_CMP_T   *)APB_CMPBase ;
CSP_OAMP_T  *OAMP     = (CSP_OAMP_T  *)APB_OAMPBase ;



/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/


